STRGeometryPar |
4 |
c0fe6f525d2b9d962114b92550b4f682 |
✘ |
✘ |
NEW |
VXDServiceGeometryPar |
3 |
c4c79c46a2d94de672b906da751b0b37 |
✘ |
✘ |
NEW |
TOPChannelMaps |
5 |
283605dc7bb3613405880f5cf2c3dbb1 |
✘ |
✘ |
NEW |
ARICHChannelMask |
12 |
783c212db6c668569ae7e9b9b0319e38 |
✘ |
✘ |
NEW |
ARICHModulesInfo |
14 |
34bf95d75bf19f94bfb8ee5b108df3ad |
✘ |
✘ |
NEW |
EKLMReconstructionParameters |
4 |
5a89d903f7921287b01d6635fbd3ff42 |
✘ |
✘ |
NEW |
PXDGeometryPar |
11 |
dc92d23ae2911ed5cf50b41b94281d44 |
✘ |
✘ |
NEW |
TOPFrontEndMaps |
6 |
78c048e968cffb2f55f3ca11ed35e00e |
✘ |
✘ |
NEW |
ECLCrystalEnergyCosmic |
12 |
d124168762412a944dfe757cdf81961b |
✘ |
✘ |
NEW |
ECLCrystalEnergyMuMu |
5 |
eaae83ea6633000d03016a4f4278d771 |
✘ |
✘ |
NEW |
ECLExpMuMuE |
5 |
e3691fc79a2f220db95d5935fe2ee4cf |
✘ |
✘ |
NEW |
KLM_fBDT_10xbkg100k |
14 |
e657812030726801c8cb214d6197de69 |
✘ |
✘ |
NEW |
SVDChannelMapping.xml |
12 |
c21520e51909fb02c86f27ef2ff5e205 |
✘ |
✘ |
NEW |
SVDNoiseCalibrations |
31 |
2faf60a8e19f5356b89c2bc743331f51 |
✘ |
✘ |
NEW |
EKLMTimeCalibration |
13 |
bbfa952cfdbd76e676b82cbf90367d16 |
✘ |
✘ |
NEW |
EKLMDisplacement |
11 |
c8c0acd67e5684579348e7964a3772b7 |
✘ |
✘ |
NEW |
ARICHMergerMapping |
14 |
bbe43acf70cd9d601abd8d56e675a4d0 |
✘ |
✘ |
NEW |
CDCBadWires |
43 |
cfa647919478ac5a11a3fbd27e919bde |
✘ |
✘ |
NEW |
CDCChannelMaps |
56 |
5ebef7ca554647e6bc6c18697a34383f |
✘ |
✘ |
NEW |
CDCPropSpeeds |
37 |
2169a6562acb48dd3b017e83f119ddcc |
✘ |
✘ |
NEW |
BKLMBadChannels |
4 |
35e63cdf1972ed2fa683f1ef5cdecef1 |
✘ |
✘ |
NEW |
EKLMSimulationParameters |
5 |
860b9a56715c1aec4c4b956099d35f2a |
✘ |
✘ |
NEW |
ECL_FPGA_HitThresh |
1 |
6ea151acd0fc17f98e3fa460c281effc |
✘ |
✘ |
NEW |
ECL_FPGA_LowAmp |
1 |
be5aefb32b367ed87e3a22f151d46e85 |
✘ |
✘ |
NEW |
ECL_FPGA_StoreDigit |
1 |
3d407b2cdbef499946718f6a9bed2929 |
✘ |
✘ |
NEW |